The present invention relates to a construction of a channel region of an insulating gate field effect transistor (hereinafter referred to as a MISFET) constituting a semiconductor device of an integrated circuit and more particularly to a semiconductor device in which a surface inversion voltage (threshold voltage) of the channel region which is determined by impurity concentrations and thicknesses of a gate insulating film of the channel region is controlled.
The present invention relates to a semiconductor device of an integrated circuit composed of MISFETs having a plurality of threshold voltages on the same substrate and to a manufacturing method thereof.
The present invention relates to a semiconductor device of an integrated circuit having different conductive MISFETs on the same substrate and to a manufacturing method thereof.
The present invention relates to a semiconductor device of an integrated circuit having high withstand voltage and low voltage MISFETs to which different gate voltages are applied on the same substrate and to a manufacturing method thereof.
The present invention relates to a semiconductor device comprising an analog circuit and a digital circuit on the same substrate and to a manufacturing method thereof.
The present invention relates to a semiconductor device formed on a thin film semiconductor provided on an insulating layer and to a manufacturing method thereof.
FIGS. 38A through 38C are schematic plan views representing MISFETs within a prior art semiconductor device of an integrated circuit.
Note that the explanation of the present specification is made exemplifying a MOSFET in which an insulating layer interposed between a metal gate electrode and a semiconductor substrate is a silicon oxide film, as a typical example of the MISFET.
FIGS. 38A to 38C schematically show a source, drain and gate of three kinds of transistors, and aluminum metallic wirings and others are omitted to simplify the description.
Transistors 1, 2 and 3 have each different threshold voltage (V.sub.TH).
FIG. 39 is a schematic section view illustrating the MOSFET within the prior art semiconductor device of the integrated circuit.
In the transistor 1, an impurity concentration of a channel region 4004 is set at a value of an impurity concentration of a semiconductor substrate 4006 and a threshold voltage determined by the impurity concentration of the channel region 4004 and a thickness of a gate insulating film 4005 is denoted as V.sub.TH1.
When it is desired to differentiate a threshold voltage V.sub.TH2 of the second transistor 2 from V.sub.TH1, a channel region 2 having an impurity concentration which is different from that of the channel region 1 of the transistor 1 is formed by optically patterning a photoresist by using a glass mask and others for selecting a region to which an impurity is doped (photolithographic technique) and by doping the impurity via the gate insulating film 4005 by ion implantation and others using the photoresist selectively formed as a mask.
At this time, a pattern 3905 of the glass mask 1 for ion implantation for selecting the region to which the impurity is doped is created so as to be slightly larger than the channel region to cover the whole surface thereof considering a dislocation of registration of the glass mask as shown in FIG. 38B and the photoresist is removed slightly more than the channel region to dope the impurity to the channel at the region where the photoresist is removed.
The gate insulating film 4005 is normally formed of a silicon oxide film having a homogeneous thickness from around 10 nm to 100 nm.
By constructing as described above, the transistor 2 having V.sub.TH2 which is different from V.sub.TH1 of the transistor 1 may be formed. In the same manner, a transistor having a necessary threshold voltage may be formed by doping a necessary impurity like V.sub.TH3 of the transistor 3.
Further, although not shown in the figure, in a semiconductor device of an integrated circuit in which a high voltage MOSFET having a thick gate oxide film and a low voltage MOSFET having a thin gate oxide film are provided on the surface of the same substrate, a concentration of a homogeneous impurity region of channel region of each MOSFET is controlled by a photolithographic technique in order to equalize each threshold voltage to almost the same value.
Similarly, in a CMOS type integrated circuit comprising P-type and N-type MOSFETS, threshold voltages are equalized to almost the same value by separate impurity doping processes.